Journal: IEICE TRANSACTIONS on Electronics Vol.E93-C No.5 pp.658-661, 2010
Title: Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device
Authors: Soo Han CHOI, Young Hee PARK, Chul Hong PARK, Sang Hoon LEE, Moon Hyun YOO, Jun Dong CHO, and Gyu Tae KIM
Summary: With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.
# 코스웍 기간 동안 학교에서 배운 지식을 바탕으로 회사에서 연구했던 width edge effects (narrow width effects) 보정 통한 leakage current 최적화 관련 논문이 일본 전자공학 저널인 IEICE TRANSACTIONS on Electronics (SCIE급)에 게재되었습니다. 그간 도움 주셨던 교수님및 연구실 멤버들에게 감사의 말씀 전합니다.
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